1. Field of the Invention
The present invention relates to radar timing circuits and more particularly to precision swept delay circuits for expanded time ranging systems. It can be used to correct errors in a swept-delay clock for sampling radar, Time Domain Reflectometry (TDR) and laser systems.
2. Description of Related Art
High accuracy pulse-echo ranging systems, such as wideband and ultra-wideband pulsed radar, pulsed laser rangefinders, and time domain reflectometers, sweep a timing circuit across a range of delays. The timing circuit controls a receiver sampling gate such that when an echo signal coincides with the temporal location of the sampling gate, a sampled echo signal is obtained. The echo range is then determined from the timing circuit, so high accuracy timing is essential. A stroboscopic time expansion technique is employed, whereby the receiver sampling rate is set to a slightly lower rate than the transmit pulse rate to create a stroboscopic time expansion effect that expands the apparent output time by a large factor, such as 100,000. Expanded time allows vastly more accurate signal processing than possible with realtime systems.
A common approach to generate accurate swept timing employs two oscillators with frequencies FT and FR that are offset by a small amount FT−FR=Δ. In a ranging application, a transmit clock at frequency FT triggers transmit pulses, and a receive clock at frequency FR gates the echo pulses. If the receive clock is lower in frequency than the transmit clock by a small amount Δ, the phase of the receive clock will slip smoothly and linearly relative to the transmit clock such that one full cycle is slipped every 1/Δ seconds. Such a clock system forms a swept phase clock system. The term phase can also relate to time, since phase is another way to express time difference between the two clocks. Typical parameters are: transmit clock FT=2 MHz, receive clock FR=1.99999 MHz, frequency offset Δ=10 Hz, phase slip period=1/Δ=100 milliseconds, and a time expansion factor of FT/Δ=200,000. This two-oscillator technique was used in the 1960's in precision time-interval counters with sub-nanosecond resolution, and it appeared in a short-range radar in U.S. Pat. No. 4,132,991, “Method and Apparatus Utilizing Time-Expanded Pulse Sequences for Distance Measurement in a Radar,” by Wocher et al.
There are many influences that can affect the accuracy of the phase slip, including: (1) oscillator noise due to thermal and flicker effects, (2) transmit-to-receive clock cross-talk, and (3) thermal transients that typically do not track out between the two oscillators. The receive oscillator is typically locked to the offset frequency by a phase locked loop (PLL) circuit, which does a reasonable job when the offset frequency is above several hundred Hertz. Unfortunately, precision long range systems require extremely high accuracy, on the order of picoseconds, at offset frequencies on the order of 10 Hz. A PLL system cannot meet this requirement for the simple reason that the PLL loop response must be slower than 1/Δ, or typically slower than 100 ms, which is far too slow to control short term phase errors between the two clocks.
U.S. Pat. No. 6,404,288 to Bletz et al addresses the problems associated with controlling low offset frequencies by introducing three additional oscillators into a system further comprised of seven counters and two phase comparators, all to permit PLL control at higher offset frequencies than the final output offset frequency, which is obtained by frequency down-mixing. This system is too complex for many commercial applications and like the prior art, it does not control instantaneous voltage controlled oscillator (VCO) phase errors and crosstalk.
Swept timing can also be implemented using analog sweep techniques. Analog approaches to swept timing include: (1) an analog voltage ramp that drives a comparator, with the comparator reference voltage controlling the delay, or (2) a delay locked loop (DLL), wherein the delay, or phase, between transmit and receive clocks is measured and controlled with a feedback loop. Examples of DLL architectures are disclosed in U.S. Pat. No. 5,563,605, “Precision Digital Pulse Phase Generator” by the present inventor, Thomas Edward McEwan, and in U.S. Pat. No. 6,055,287 “Phase-Comparator-Less Delay Locked Loop”, also by the present inventor. The analog approaches are subject to component and temperature variations, and often require calibration during manufacture. There can also be accuracy limitations.
A radar timing system employing a direct digital synthesizer (DDS) is disclosed in U.S. patent application Ser. No. 11/351,924, “Direct Digital Synthesis Radar Timing System” by the present inventor. A DDS generates frequencies by digitally accumulating phase in a manner that directly emulates the definition of frequency. Frequency ω can be defined by a rate of change in phase φ or ω=φ/t, where t is time. Direct digital synthesis emulates this process by continually incrementing a digital phase value in discrete phase increments in a phase accumulator. It performs the accumulation in discrete time steps. The size of the discrete phase increment is set by a digital tuning word, and the discrete time steps are set by a DDS clock. Together, both define the synthesized frequency. This technique works well for low synthesized frequencies relative to the DDS clock frequency since a large number of small phase increments can be added in the phase accumulator to produce one full cycle spanning 0 to 2 π in phase, and a very smooth progression in phase can be realized. It does not work as well at higher frequencies that are required for radar.
In a radar system, a DDS drives a receive sampling gate at a frequency that is offset from a transmit pulse frequency to produce an expanded time sampled echo signal. The frequency offset generates a smoothly slipping phase between realtime received echoes and the sampling gate that stroboscopically expands the apparent time of the sampled echoes with an exemplary factor of 1-million and a range accuracy of 1-centimeter. The flexibility and repeatability of the digitally synthesized timing system is a quantum leap over analog prior art. However, the accuracy of currently available DDS chips is limited to about 0.05% of full scale range. Many applications require higher accuracy but cannot take advantage of the benefits of a DDS timing system due to limited accuracy.
A rate locked loop (RLL) timing system is disclosed in U.S. patent application Ser. No. 11/343,049, “Rate Locked Loop Radar Timing System” by the present inventor. An RLL regulates phase slip between two clock signals to provide precision timing for radar, TDR and laser ranging systems. A phase detector converts clock phase to voltage and the voltage is differentiated to provide a rate-of-change signal to a loop controller that precisely regulates the rate-of-phase change. The RLL controls a VCO to produce a constant, linear phase slip having phase errors below the time equivalent of 1-picosecond. However, the RLL lacks the repeatability and programmability of a digital timing system such as a DDS.